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2016 Session Descriptions

Wednesday, April 13th
8:30-9:45am
Session A-101: Scale-Out Servers (Compute Track)
Organizers: Chris Piedmonte, CEO, Suvola; Paul Teich, Sr Analyst, Tirias Research
Chairperson: Chris Piedmonte, CEO, Suvola
Instructors:
Low Latency Video Analytics with Scale-Out Servers
Devashish Paul, Director Strategic Marketing – Systems Solutions, IDT
Scale-Out Servers Reduce Energy Costs Significantly
Brian Zahnstecher, Principal, PowerRox
Examining Server-on-Chip (SoC) Devices for Scale-Out Computing
Kumar Sankaran, Associate VP, Applied Micro
Workload Optimized Scale-Out Servers for Emerging Cloud Platforms
Rishi Chugh, Director Product Marketing, Cavium
Measuring Scale-Out Server Performance: Tradeoffs and Issues
Markus Levy, President, EEMBC
Description:
Scale-out servers are high-density, low-power, low-cost devices that operate best in applications that can run in parallel with little coordination. One prominent example is large-scale web services (such as social networks) that deploy many servers to perform simple tasks. Other possible applications include big data analytics (Hadoop-in-a-box), signal processing, software-as-a-service (SaaS), and clouds. Issues include efficient server management and the identification of suitable applications.
Intended Audience:
Hardware and software designers, engineering managers, server designers, systems and software engineers, systems analysts and integrators, marketing and product engineers and managers, technology managers, test engineers, network and server managers and engineers.
About the Chairperson:
Chris Piedmonte is CEO of Suvola, a company focused on creating enterprise-class software and offering engineering and consulting services for scale-out servers. He was previously cofounder and CTO of Algebraix Data, and founder/CEO of XSPRADA, where he developed enterprise data management software. He was also founder/CEO of Eagle Creek Systems, which he built into a multimillion-dollar software engineering business. He holds 8 patents in data management. An expert in software technologies such as object-oriented analysis and design, applications and systems design, and development and project management, he has a BSEE from the Rose-Hulman Institute of Technology.
8:30-9:45am
Session B-101: Open-Source Switching and SDN (Networking Track)
Organizers: Christos Kolias, Researcher, Orange Silicon Valley; Peter Christy, Research Director Networking, 451 Research
Chairperson: Craig Matsumoto, Managing Editor, SDxCentral
Instructors:
Introduction to Open Source Switching
Peter Christy, Research Director Networking, 451 Research
Software Ecosystem Fragmentation : Generating Headwinds for White ABox Switching Market Growth
Bharat Mota, Director Software, NXP Semiconductors
Open SDN Deployments for Physical Networks
Arkadiy Shapiro, Principal Technical Marketing Engineer, Big Switch Networks
Description:
Open-source switching brings the open source concept to network switching. It means that basic designs and the software stack are available to everyone royalty-free. Facebook’s Open Compute Project has taken the lead here with the first design being for a top-of-rack switch. The idea is to handle the physical realities and then let vendors innovate in software. Users would then be able to change vendors or combine hardware from multiple vendors without being locked into proprietary code. It fits well with such emerging approaches as scale-out servers, software-defined networking (SDN), and software-defined storage.
SDN is THE hottest topic in networking today, with analysts predicting a multibillion dollar market opportunity, startups attracting huge investments, and networking OEMs and operators alike reassessing their business models in the face of a major transformation. A new architecture is needed to address the networking challenges imposed by spiraling multimedia traffic growth, mobile everything, and user expectations for any data anywhere at any time. SDN offers the promise of highly scalable and flexible networks that provide agility, operating efficiency, and lower overall costs
Intended Audience:
Systems analysts and engineers; computer, network, and data center engineers; storage, communications, and server specialists; cloud computing specialists; engineering managers; technology managers; test engineers; performance analysts.
About the Chairperson:
Craig Matsumoto is Managing Editor at SDxCentral.com, responsible for the site's content and for covering news. He was previously West Coast Editor for Light Reading, covering routers, Carrier and high-speed Ethernet, optical networking, cloud computing, and semiconductors. Among Silicon Valley’s most highly respected technical journalists, he joined Light Reading in 2002. He previously spent seven years with EE Times, focusing on semiconductors and optical networking. He has also written for the San Jose Business Journal and the Fresno Business Journal.
8:30-9:45am
Session C-101: NVM Storage (Storage/Performance Track)
Organizers: Uma Parepalli, Architect, SK Hynix Memory Solutions; Jonathan Hinkle, Director/System Platform Technologist, Lenovo
Chairperson: Uma Parepalli, Architect, SK Hynix Memory Solutions
Instructors:
New Supercapacitor Technology Increases Energy Density for NVRAM Backup
Gene Armstrong, Director Applications, Paper Battery
Designing Effficient Enterprise Systems in the SSD Era
Hubbert Smith, Strategy and Business Development Director, Samsung Semiconductor
Getting Started with NVMe SSD Software Development
Uma Parepalli, Architect, SK Hynix Memory Solutions
Description:
Solid state memory is rapidly replacing hard drives in many storage systems. The advantages are obvious – solid state memory is smaller, more rugged, lower power, faster, easier to interface, more flexible, and easier to handle. When configured as a solid state drive (SSD), it can be a drop-in replacement for a hard drive, thus taking advantage of existing software. However, disk interfaces limit SSD speed, so designers have been looking at alternatives such as PCIe with the NVMe storage extensions. PCIe is another well-known, widely supported interface that supports much higher data rates than SAS or SATA.
Intended Audience:
Systems analysts and engineers; computer, network, and data center engineers; storage, communications, and server specialists; cloud computing specialists; engineering managers; technology managers; test engineers; performance analysts.
About the Chairperson:
Uma Parepalli is a Storage Architect currently focusing on PCIe NVMe firmware, UEFI BIOS, and hardware-software co-design and development. He is SK Hynix’s organizational representative for industry standards groups, including NVM Express, UEFI, and ACPI. . Uma previously worked for such companies as EMC, LSI, Dell, Intel, and Wipro and continue to collaborate with every major OEM, OS, BIOS, and device vendor. He has over 24 years experience in the aerospace, consumer electronics, semiconductor and storage industries in architecture and senior management roles leading global engineering teams. Uma won awards for his work with the Departments of Defense and Space in India. He has also led global diversity teams for EMC and Intel and was an American Red Cross Disaster Action Team Captain. He is a Computer Engineering graduate of the University of Mysore, India.
8:30-9:45am
Session D-101: Advances in High-Speed Interfaces (Technology Breakthroughs Track)
Organizers: Brian Zahnstecher, Principal, PowerRox; KRS Murthy, CEO, I Cubed
Chairperson: Peter Scruton, Manager, UNH-IOL
Instructors:
Developing High-Speed Server Interconnects at 25/50 Gbps
Arash Behziz, Technologist, TE Connectivity
The Universal Server Interconnect
Debendra Das Sharma, Sr Principal Engineer/ Director, Intel, PCIe 4.0 Technology
100GbE Single Lambda Technology for Data Center Connectivity
Avi Shabtai, MultiPhy
Description:
Advances continue in all aspects of high-speed interfaces. At the physical level, efforts continue to go beyond current levels of 10 and 25 Gbps signaling. Such work is essential to reduce the number of lanes required to implement standards at 50 Gb and above. Meanwhile, other widely used standards also keep advancing with the popular PCIe interface now having a 4.0 version with double the bandwidth of its predecessor.
Intended Audience:
Communications engineers; hardware design engineers and managers; product planners and designers; network engineers and managers; communications and networking specialists; system architects and engineers.
About the Chairperson:
Peter Scruton is a Manager Embedded Systems Technologies at the University of New Hampshire InterOperability Lab (UNH-IOL). Peter has 19 years experience in Ethernet conformance and interoperability testing. He currently works on test tool research and development, enabling the testing of Interspersing Express Traffic and Time-Sensitive Networking (TSN). He is also updating and expanding a Layer 2 Ethernet Test Tool. He has been a speaker and panelist at several Ethernet Technology Summits on subjects such as data center bridging (DCB) and the future of Ethernet networks. He earned a BS in computer science from the University of New Hampshire.
10:00-11:00am
Session A-102: Future of Scale-Out Servers (Compute Track)
Organizers: Chris Piedmonte, CEO, Suvola; Paul Teich, Sr Analyst, Tirias Research
Chairperson: Jag Bolaria, Principal Analyst, Linley Group
Panelists:
Chris Piedmonte, CEO, Suvola
Kumar Sankaran, Associate VP, Applied Micro
Devashish Paul, Director Strategic Marketing – Systems Solutions, IDT
Rishi Chugh, Director Product Marketing, Cavium
Jeff Underhill, Director Server Programs, ARM
Description:
Scale-out servers are high-density, low-power, low-cost devices that operate best in applications that can run in parallel with little coordination. One prominent example is large-scale web services (such as social networks) that deploy many servers to perform simple tasks. Other possible applications include big data analytics (Hadoop-in-a-box), signal processing, software-as-a-service (SaaS), and clouds. Issues include efficient server management, the identification of suitable applications, software development, and communications among devices. The application issue is currently the most pressing one, since only a few highly specialized applications have so far emerged for which this form factor offers clear advantages.
Intended Audience:
Hardware and software designers, engineering managers, server designers, systems and software engineers, systems analysts and integrators, marketing and product engineers and managers, technology managers, test engineers, network and server managers and engineers.
About the Chairperson:
Jag Bolaria is a principal analyst for embedded and servers at The Linley Group. During more than 20 years in the communications and PC semiconductor industries, he defined and launched products for computing and networking that shipped more than 100 million units. He is the coauthor of many Linley Group publications, has spoken at many events, and has written application notes for EDN and other magazines. Before joining The Linley Group, Jag was the director of network systems and validation for Intel’s Ethernet components. He also was Director of Marketing for chipsets at Intel, where he led the development of product plans, design wins, and customer support for the Pentium and P6, working with all major PC and server suppliers worldwide. He has previous experience with Intel’s communications group and Standard Telecom Labs. He holds a BS in Electronics with Honors from the University of Salford (UK).
10:00-11:00am
Session B-102: Future of Open-Source Switching (Networking Track)
Organizers: Christos Kolias, Researcher, Orange Silicon Valley; Peter Christy, Research Director Networking, 451 Research
Chairperson: Peter Christy, Research Director Networking, 451 Research
Panelists:
Bharat Mota, Director Software, NXP Semiconductors
David Meyer, Chief Scientist/Fellow, Brocade Communications
Arkadiy Shapiro, Principal Technical Marketing Engineer, Big Switch Networks
Ajay Dubey, System Architect, Altera
Description:
Open-source switching brings the open source concept to network switching. It means that basic designs and the software stack are available to everyone royalty-free. Facebook’s Open Compute Project has taken the lead here with the first design being for a top-of-rack switch. The idea is to handle the physical realities and then let vendors innovate in software. Users would then be able to change vendors or combine hardware from multiple vendors without being locked into proprietary code. It fits well with such emerging approaches as scale-out servers, software-defined networking (SDN), and software-defined storage.
Intended Audience:
Systems analysts and engineers; computer, network, and data center engineers; storage, communications, and server specialists; cloud computing specialists; engineering managers; technology managers; test engineers; performance analysts.
About the Chairperson:
Peter Christy is currently Research Director Networking at 451 Research Group. He has recently been studying OpenFlow from the perspective of existing systems, as well as networking companies and new ventures. Previously, he co-founded the Internet Research Group (IRG), a boutique consultancy that provides strategy and marketing services to technical ventures and enterprises. IRG worked with companies whose products depend on both network and system capabilities in disruptive or emerging markets. Before founding IRG, Peter worked in technology and strategy roles at major computer companies including DEC, IBM/Rolm, HP, Apple, and Sun. He was a founder and VP Software at MasPar Computer. He has an AB from Harvard and did graduate work in EECS at UC Berkeley.
10:00-11:00am
Session C-102: Open Storage/Open Networking (Storage/Performance Track)
Organizers: Uma Parepalli, Architect, SK Hynix Memory Solutions; Jonathan Hinkle, Director/System Platform Technologist, Lenovo
Chairperson: David Woolf, Sr Engineer, UNH-IOL
Instructors:
Six Reasons Why You Must Use Open Source Storage Technology
Michael Dexter, Sr Analyst, iXsystems
Using Optimized Processors to Improve SDN/NFV Performance
Debasish Pratiher, Lead Sr Technical Marketing Engineer, Cavium
Ultra HD Video Encoding at Scale
Tom Vaughan, VP/GM Video, Multicoreware
Description:
Open is the key term in developing hyperconverged systems. When megadatacenters are dealing with millions of units, everything has to be as simpler and cheap as possible. No one can afford the extra costs of branded items, proprietary software or hardware, or customization. Everything needs to be scalable, so the megadatacenters can expand to meet rapidly increasing requirements for compute, networking, and storage.
Intended Audience:
Systems analysts and engineers; computer, network, and data center engineers; storage, communications, and server specialists; cloud computing specialists; engineering managers; technology managers; test engineers; performance analysts.
About the Chairperson:
David Woolf is Senior Engineer Datacenter Technologies at the University of New Hampshire InterOperability Laboratory (UNH-IOL). He has developed dozens of industry-reviewed test procedures and implementations as part of the team that has grown the UNH-IOL into a world-class center for interoperability and conformance testing. David has also helped organize many industry test events.

David has been an active participant in industry forums and committees addressing conformance and interoperability, including the SAS Plugfest Committee, SATA-IO Logo Workgroup, and MIPI Alliance Testing Workgroup. He also coordinates the Integrators List and plugfest programs for NVMe and Open Networking. He earned a BSEE from the University of New Hampshire.
10:00-11:00am
Session D-102: The 400GbE Standard (Technology Breakthroughs Track)
Organizers: Brian Zahnstecher, Principal, PowerRox; KRS Murthy, CEO, I Cubed
Chairperson: Brian Zahnstecher, Principal, PowerRox
Instructors:
The 400GbE Standard: What It Will Mean for Designers
Shre Shah, Data Center Architect, Xilinx
PAM4: The Right Modulation Scheme for High-Performance Ethernet
Scott Feller, Associate VP Product Marketing, Inphi
Description:
The 400GbE project now has a draft standard, and the key features for designers are becoming clearer.  In the first place, reasonable implementations (fewer than 16 lanes) will require 50 Gb/s signaling (also needed for intermediate standards at 50 GbE, 100 GbE, and 200 GbE).  Such high rates mean that forward error correction (FEC) is required, and PAM4 signaling comes into play.  Even serial 100G wavelengths are being supported.  Designers can expect to see added complexity, higher latency, more signal integrity problems, and a need for higher-frequency (and far more expensive) test equipment, components, coprocessors, and prototyping circuits.
Intended Audience:
Communications engineers; hardware design engineers and managers; product planners and designers; network engineers and managers; communications and networking specialists; system architects and engineers.
11:00-11:30am
Tom Bradicich photo
OPEN - Keynote 1: Managing Enormous Data from the Internet of Things
Speaker: Tom Bradicich, GM/VP, Servers/IoT Systems, Hewlett Packard Enterprise
Introduction: Jonathan Hinkle, Director/System Platform Technologist, Lenovo
Abstract:
How the Internet of Things (IoT) will play out is still uncertain, but we do know the "things" will produce huge amounts of data. Since the amounts will be more than anyone can manage easily, we must look at how to process and store it in new ways. Workload-optimized, scalable, industry-standard servers will play a key role in end-to-end IoT solutions, in which analytics on the data can be executed in several compute domains. The systems must be scaled-in or scaled-out to meet the demands of many diverse applications, and render new business, engineering, and scientific insight from the data. To achieve desired business results, compute solutions at the IoT edge must reach new levels in performance, cost, durability, and energy consumption, all coupled with open augmentable software from both vendors and the open source community.
About the Speaker:
Dr. Tom Bradicich is VP/GM Servers/IoT Systems at Hewlett Packard Enterprise (HPE), where he leads the global business unit for dense scalable servers and IoT Systems, with P&L ownership, product development, and customer experience worldwide. He and his team also direct the HPE Discovery Labs for partner and customer collaborations on systems and solutions. Tom’s systems received an InfoWorld 2015 Technology of the Year Award, ARM TechCon Best of Show, and a CRN 2015 Product of the Year Award. He was previously VP Server Engineering at HP, responsible for global R&D and delivery of the workload optimized, converged server product line. Tom and his staff directed several worldwide engineering teams, releasing over 20 products and integrated solutions stacks. They pioneered the first Intel Xeon™ server with on-chip integrated graphics, and the first 64 bit enterprise ARM server.

He has also been an R&D Fellow and Corporate Officer at National Instruments (NI) where he led teams developing end-to-end solutions based on data acquisition and analysis systems and IT infrastructures for the test, measurement, and control industries. Before joining NI, Tom was an IBM Fellow, Vice President of Systems Technology, Distinguished Engineer, Engineering Director, and CTO for IBM’s x86 server and converged systems lines. He managed the architectural design of scale-up x86 SMP servers, and received the IBM Chairman’s Award for his role in pioneering enterprise blade servers. Tom was elected to the IBM Academy of Technology and co-founded several technical industry standards groups, including PCI SIG, DMTF SMASH, The Green Grid, and Blade.org. He holds several patents in PC and server design. He earned a BSEE from Florida Atlantic University, an MS from North Carolina State University, and a PhD from the University of Florida. He has served on several university adjunct faculties.
About HP Enterprise:
More information is available at HP Enterprise.com.
11:30am-Noon
Kushagra Vaid photo
OPEN - Keynote 2: Innovating in the Cloud at Hyperscale
Speaker: Kushagra Vaid, GM Server Hardware Engineering, Microsoft
Introduction: Jacob Hall, Sr VP/Innovation Wrangler, Wells Fargo
Abstract:
Large cloud operators must build out the most advanced infrastructures to deliver great services to customers and to compete in the marketplace. So they must constantly look for ways to innovate, while at the same time optimizing for cost and performance. Rapid changes in cloud workloads have led to new computing models involving diverse system architectures. For example, cloud servers may need to use FPGAs to accelerate encryption and flow control of network traffic. This talk will cover the latest server innovations aimed at large scale cloud computing and will provide insight into the future of cloud infrastructures.
About the Speaker:
Kushagra Vaid is the General Manager for Server Engineering in Microsoft’s Cloud and Enterprise division. He is responsible for driving hardware R&D, engineering designs, deployments, and support for Microsoft’s cloud scale services, such as Bing, Azure, and Office 365, across global datacenters. The engineering effort also includes development for the OpenCloud Server (OCS) specification that Microsoft contributed to the Open Compute Project (OCP).

Kushagra joined Microsoft in 2007 as Principal Architect working on improving performance/power ratios for large cloud services, and contributed to the development of standardized energy efficiency benchmarks at the SPEC and TPC industry forums. He was also responsible for driving Microsoft’s datacenter hardware strategy and cloud optimized server designs, working closely with the broader hardware industry. Before joining Microsoft, Kushagra was a Principal Engineer at Intel where he drove the technology direction for Xeon microprocessors and platforms. He started his career as a CPU design engineer working on enterprise class CPUs and platforms.

Kushagra has presented several papers at international research conferences, and holds over 25 patents in computer architecture and datacenter design. He has been a featured speaker at industry conferences on cloud services, hardware engineering, and datacenter architecture. He has an MS in Computer Science from SUNY Binghamton and a BE in Computer Engineering from the University of Mumbai (India).
About Microsoft:
More information is available at Microsoft.com.
1:30-1:40pm
Frank Berry photo
OPEN - Special Presentation 1: IT Brand Pulse Key Awards
Speaker: Frank Berry, President/Chief Analyst, IT Brand Pulse
Abstract:
The IT Brand Pulse awards are the symbols for brand leadership; covering hundreds of IT categories each year – from servers, storage and networking to cloud, software and other broad IT market segments.
Measuring the perceptions of IT professionals from large enterprise, medium enterprise and HPC environments, winners are voted in surveys that are independent, non-sponsored research.

The surveys are designed to capture the pulse of brand leadership in different product categories. For each survey, IT Pros are asked to vote for Market, Innovation, Performance, Reliability, Service & Support, and Price leaders from a randomized field of provided vendors (or the opportunity to write in an answer choice).
About the Speaker:
A 30-year veteran of the IT industry including senior executive positions with QLogic and Quantum, Frank founded IT Brand Pulse and leads the Business Development practice. The “Biz Dev” team helps clients create demand for their products and services through PR, advertising, trade shows, on-line events, channel programs and IT education. Frank also contributes industry analysis to leading IT publications and as a keynote speaker.
About IT Brand Pulse:
More information is available at IT Brand Pulse.
1:40-2:10pm
John D'Ambrosia photo
OPEN - Keynote 3: Building on Ethernet’s New Diversity
Speaker: John D’Ambrosia, Chairperson, Ethernet Alliance/Sr Principal Engineer, Huawei/Chair, IEEE P802.3bs 400GbE Task Force
Introduction: Frank Berry, President/Chief Analyst, IT Brand Pulse
Abstract:
Today’s Ethernet consists of a series of specifications that address diverse application spaces.   Solutions range from operation over copper traces for a few millimeters to optical fibers that range up to 40 km.  At the top end, higher signaling rates require new modulation methods, such as PAM4.  New standards always require system cost and performance tradeoffs, as well as ensuring the availability of connectors, board materials, components, cabling, and other parts.  System designers will face new challenges in employing the latest series of specifications, but they will also find an arsenal of tools for the development of the next generation of Ethernet equipment.  
 
Having so many interfaces to support is a mixed blessing.  There are now many interoperability issues, as well as a need for varied test methods, test equipment, and associated hardware and software.  However, designers will also find they have the right tools for both traditional and emerging applications, as well as ones not yet even imagined.
About the Speaker:
John D’Ambrosia s the single most widely recognized figure in the development of new Ethernet standards. In his role as a Senior Principal Engineer at Huawei, he leads the drive toward higher rates and other advances. Currently, he chairs the IEEE P802.3bs 400GbE Task Force, is a member of the IEEE 802 Executive Committee, and chairs the IEEE 802.3 Industry Connections Next Generation Enterprise / Data Center / Campus (ECDC) Ad Hoc, a forum for exploring new ideas for Ethernet standards. Previously, he chaired the IEEE 802.3ba Task Force that developed 40GbE and 100GbE. He is also the Chairman of the Ethernet Alliance, an organization dedicated to the promotion of all Ethernet technologies, and a popular blogger on Ethernet matters. In 2013 D’Ambrosia was awarded the IEEE-SA 2013 Standards Medallion and was inducted into the Light Reading Hall of Fame. He has previous experience with Dell, Force10 Networks, and Tyco Electronics.
About Ethernet Alliance:
For more information, see Ethernet Alliance.
2:10-2:40pm
Greg Pruett photo
OPEN - Keynote 4: Up in the Air: Making an Effective Transition to Cloud Computing
Speaker: Greg Pruett, Executive Director/Distinguished Engineer, Lenovo
Introduction: Chris DePuy, VP, Dell’Oro Group
Abstract:
Enterprise data centers are rapidly discarding their traditional role as providers of on-premise computing. They now are moving toward being largely users of private and public clouds instead of their own facilities. The transition requires a change from today’s largely fragmented management processes to well-orchestrated software-defined approaches that optimize distributed resources to meet the needs of workloads or applications. Hyperconverged infrastructure, software-defined networking and storage, and unified service management, plus a resurgence of leveraging bare-metal facilities, are the leading server-based solutions datacenters are adopting to address the imminent challenge.
About the Speaker:
Greg Pruett is Executive Director/Distinguished Engineer/Chief Architect Enterprise Systems for the Lenovo Enterprise Business Group (EBF). He also leads the enterprise Strategic Technologies Innovation Center, where he focuses on creating innovation that truly matters to customers. As Chief Architect, he has overall responsibility for the design of Lenovo enterprise systems and software, including both traditional datacenter and new software-defined strategies. He is a Master Inventor with 48 issued or pending patents in such areas as systems management, blade server technology, and automated provisioning.

Before joining Lenovo, he was Chief Architect at IBM, where he led the architecture and development of software and firmware for PureFlex, IBM’s first converged system. He worked at IBM for over 18 years. He is the author of many technical publications and conference presentations and a member of the DMTF Board of Directors. Greg holds a Master’s degree in computer science from the University of North Carolina at Chapel Hill and a Bachelor’s degree with majors in mathematics and computer science from Furman University.
About Lenovo:
More information is available at Lenovo.com.
3:00-4:00pm
Session A-103: Application Acceleration (Compute Track)
Organizers: Chris Piedmonte, CEO, Suvola; Paul Teich, Sr Analyst, Tirias Research
Chairperson: Kiran Gunnam, Technologist, Western Digital
Instructors:
Using Coprocessors to Accelerate Analytics
Debabrata Sarkar, Sr Engineering Manager, Oracle
Optimize Your Code for Better Performance on Linux
Shayam Prakasha, Mgr/Software Development, Citrix R&D India
Application Acceleration on Open Server Platforms
Sam Nemazie, CTO, Prossimo Technology
Hardware Compression Accelerates Big Data Applications
Juan Deaton, Research Scientist, Comtech AHA
Implementing Ultra Low Latency Data Center Services with Programmable Logic
John Lockwood, CEO, Algo-Logic
Description:
Many database applications, particularly Oracle and Hadoop, are notoriously slow performers. There are many ways to make them run faster, ranging from minimizing data movement and reducing networking overhead to hardware acceleration and in-memory execution. Other approaches include code optimization, simply adding more servers, and hardware compression. This session will explore several recent advances in application acceleration.
Intended Audience:
Hardware design engineers; engineering managers; product and product marketing engineers; storage engineers, specialists, and managers; data center engineers and managers; network engineers and managers; CIOs, CTOs, and infrastructure architects; IT managers; product planners and designers; VARs, OEMs, and solution providers; system analysts, engineers, and managers; market analysts; marketing managers and marketing engineers.
About the Chairperson:

Kiran Gunnam is a Technologist in Western Digital’s Storage Architecture Research Group, where he focuses on creating and developing new storage and computing related projects. He was previously Director of Engineering at Violin Memory and also held R&D positions at Nvidia, Certicom, LSI, Marvell, Schlumberger, and Intel.

Dr. Gunnam is an expert in IC implementation of communications and signal processing systems. His PhD research contributed several key innovations in advanced error correction systems based on low-density parity-check codes (LDPC) and led to several industry designs. He has done extensive work on ASIC hardware architecture, micro-architecture, and digital IC implementation for many applications (including IEEE 802.11n Wi-Fi, IEEE 802.16e WiMax, IEEE 802.3 10-GB, holographic read channel, HDD read channel, and flash read channel).

Dr. Gunnam has over 60 patents with several more pending. He was an IEEE Solid State Circuits Society Distinguished Lecturer for 2013 and 2014. He earned an MSEE and PhD in Computer Engineering from Texas A&M University.

3:00-4:00pm
OPEN - Session B-103: The 2016 Ethernet Roadmap (Networking Track)
(sponsored by the Ethernet Alliance)
Organizers: Christos Kolias, Researcher, Orange Silicon Valley; Peter Christy, Research Director Networking, 451 Research
Chairperson: Scott Kipp, Principal Technologist, Brocade Communications
Instructors:
Choosing the Right Ethernet Standard for Your Application
Dave Chalupsky, Network Hardware Architect, Intel
What Fits Where?  How Designers Should Use All the New Ethernet Speeds
Mark Nowell, Sr Director Engineering/CTO, Cisco Systems
How to Use 25/50/100G Ethernet in the Data Center
Brad Smith, Director Marketing Interconnects, Mellanox Technologies
Description:
IEEE is developing six new speeds at once and Ethernet is bursting at the seams with new applications.  As the number of networking solutions covered by Ethernet keeps expanding, Ethernet continues to evolve to meet each market such as automotive, Power over Ethernet (PoE), hard disk drives and hyperscale data centers.  Markets have now gone far beyond the LANs for which Ethernet was invented over 40 years ago.  There are now 12 rates in use or being developed for the data center with more to come.  Current issues include high-frequency design methods (10G and above), making Ethernet designs allow for multiple rates, meeting the requirements of clouds and megawebsites at reasonable cost levels, identifying roadmaps for copper and fiberoptic cabling, and creating switches that are powerful enough and flexible enough to meet the challenges of big data, mobile access everywhere, the Internet-of-Things, video networks, and real-time analysis.
About the Chairperson:
Scott Kipp is Director of Engineering at Brocade Communications Systems. He represents Brocade in multiple physical layer standards and industry associations. Kipp is the President of the Ethernet Alliance and the roadmap chair of the Ethernet Alliance and the Fibre Channel Industry Association.  He  regularly attends IEEE 802.3, OIF, T11 (Fibre Channel) and multiple other Alliances and Multi-Sourcing Agreements. He has been chair or vice-chair of such efforts as the 10x10 MSA, Quad SFP MSA, and T11.5 Task Group. He is the author of several books on Fibre Channel and other technical subjects, He also holds a patent for a terabit top-of-rack switch. Mr. Kipp has an MSEE and BSEE from Cal Poly San Luis Obispo.
3:00-4:00pm
Session C-103:   Software-Defined Storage (Storage/Performance Track)
Organizers: Uma Parepalli, Architect, SK Hynix Memory Solutions; Jonathan Hinkle, Director/System Platform Technologist, Lenovo
Chairperson: Chris DePuy, VP, Dell’Oro Group
Instructors:
All-Flash Ceph Cluster
Gunna Marripudi, Principal Architect, Samsung Semiconductor
Customizable Storage Controller Designed for SDS
Rich Fetik, CEO, Data Confidential
Description:
Storage is a continual pain point for many current deployments, particularly clouds. Software-defined storage (SDS) abstracts storage services from the hardware, thus allowing for great operating efficiency. SDS reduces management complexity and provides inexpensive scaling. Centers can use commodity hardware, as well as their existing infrastructure. SDS also allows for distribution, including storage that may actually be cloud-based.
Intended Audience:
Hardware designers, engineering managers, server designers, systems engineers, systems analysts and integrators, marketing and product engineers and managers, technology managers, test engineers, telco and enterprise end users, server managers, consultants, storage and server specialists; network engineers and managers.
About the Chairperson:
Chris DePuy is a Vice-President at Dell’Oro Group, responsible for the Carrier IP Telephony, Enterprise Edge, Wireless LAN, Wireless Packet Core, and Storage market research programs. He has over 20 years of financial analysis, business analysis, and engineering experience. He has been a consultant with TS Cap and a research analyst covering software, communications, and Internet with Bowman Capital and Morgan Stanley. He was named the top ranking Equity Research Analyst in the data networking sector by Institutional Investor and Greenwich Research Survey. The co-author of a book, he holds a Masters in engineering from Cornell and a BS in engineering from Union College.
3:00-4:00pm
Session D-103: Servers and Advanced Database Technology: (Technology Breakthroughs Track)
Organizers: Brian Zahnstecher, Principal, PowerRox; KRS Murthy, CEO, I Cubed
Chairperson: KRS Murthy, CEO, I Cubed
Instructors:
Enabling Big Data Applications to Utilize Varied Storage Resources
Bin Fan, Software Engineer, and Calvin Jia, Software Engineer, Tachyon Nexus
New Programming Platform for High-Throughput Server Applications
Don Marti, Technical Marketing Manager, ScyllaD
Description:
New hardware such as distributed servers and SSDs raises new challenges for databases. Older products are often difficult to update, leading to the need for new entries. ScyllaDB is a new approach to NoSQL data store design, optimized for modern hardware. Tachyon Nexus manages different types of storage, including memory, SSDs, and hard drives.
Intended Audience:
Systems architects and engineers; hardware and software design engineers and engineering managers; product planners and designers; network engineers and managers; communications and networking specialists; database specialists.
About the Chairperson:
KRS Murthy is an experienced venture capitalist and serial entrepreneur. He is currently focused on mergers and acquisitions, corporate governance, big data strategy, and competitive strategy. He has led many companies at many different stages and has grown companies to sales of over $500 million. He is a popular speaker at conferences around the world and a leader in many technical societies, including IEEE Nanotechnology Council, IEEE Engineering Management Society, IEEE Computer Society, Silicon Valley Engineering Council, and IEEE Standards Board.

Murthy also has experience as a Country Manager for AT&T and AT&T Bell Labs and as a professor of computer engineering at California State University, Fullerton. He has received a Distinguished Service Award from the IEEE Engineering Management Society and a Distinguished Achievement Award from the President of India.
4:00-5:00pm
OPEN - Plenary on Server Roadmaps
Chairperson: Nathan Brookwood, Research Fellow, Insight 64
Panelists:
Parag Jain, Associate VP Processor Product, Applied Micro
Norman James, Lead Engineer OpenPOWER Enablement, IBM
Jeff Underhill, Director Server Programs, ARM
Shay Gal-On, Principal Engineer, Cavium
Description:
What do the processor makers have in store for servers over the next few years? We’ll hear from several of them as to what we can expect. Their roadmaps will provide guidelines as to what must happen in the rest of the server systems to maximize performance, minimize energy consumption, and support current initiatives such as clouds, big data, software-defined networking, software-defined storage, hyperconvergence, and the software-defined data center. Processor advances will also govern general design schedules and performance estimates and analyses.
Intended Audience:
Hardware designers, engineering managers, server designers, systems engineers, systems analysts and integrators, marketing and product engineers and managers, technology managers, test engineers, telco and enterprise end users, server and data center managers, consultants, design and communications specialists, and design service providers.
About the Chairperson:
Nathan Brookwood is Research Fellow at Insight 64, a semiconductor consulting firm. He has focused recently on microprocessors used in computational applications. His views on the microprocessor market often find their way into articles in mainstream media, business media, and the trade press. He has worked for and with suppliers of mainframes, minicomputers, personal computers, and semiconductors, and he has analyzed and commented on the industry for D.H. Brown Associates and Dataquest. During his 40 year industry career, Mr. Brookwood has worked for Micronics Computers, Intergraph, Convergent Technologies, Prime Computer, and Digital Equipment. He is a graduate of MIT and has taken classes at Harvard Business School.
5:00-5:10pm
Rich Castagna  photo
OPEN - Special Presentation 2: TechTarget Server/Storage/Networking Websites
Speaker: Rich Castagna, VP Editorial, TechTarget
Abstract:
TechTarget storage websites are the best online information resource for news, tips and expert advice for the storage, backup and disaster recovery markets. Topics include SSD, backup, storage for virtual servers and cloud storage. TechTarget networking websites cover routing and switching, network security and management, application performance and delivery, VoIP, unified communications and collaboration, wireless LANs, Software Defined Networking, Wide Area Networks and mobility.
About the Speaker:
As editorial director of TechTarget's Storage media group, Rich oversees content for Storage magazine, SearchStorage.com, SearchDataBackup.com, SearchDisasterRecovery.com, SearchVirtualStorage.com, SearchCloudStorage.com, SearchSMBStorage.com and the Storage Decisions conferences. Rich has been involved with high-tech journalism for nearly 20 years; previously, he was executive editor of ZDNet Tech Update and Cnet Enterprise; editor in chief of Windows Systems magazine; senior editor for Windows magazine; and senior editor and technical editor for PC Sources. In those roles, and as a freelancer, Rich has written more than 500 computer technology articles.
About Company:
More information is available at TechTarget.
5:10-5:40pm
Kevin Deirling photo
OPEN - Keynote 5: Persistent Memory over Fabrics Revolutionizes Server/Storage Architectures
Speaker: Kevin Deierling, VP Marketing, Mellanox Technologies
Introduction: Rich Castagna, VP Editorial, TechTarget
Abstract:
New classes of non-volatile memory will revolutionize traditional server and storage architectures by combining memory-speed access with storage-like persistence. Persistent memory (PMEM) offers performance and data protection benefits to application developers, but also creates new issues for programming models and for ensuring data consistency and coherence across application and storage clusters. Applications such as in-memory databases, distributed file systems, NoSQL databases, machine learning, and hyper-converged infrastructure will benefit from PMEM only if paired with a suitable high-speed fabric. Advanced Remote Direct Memory Access (RDMA) networks offer the bandwidth, low latency, hardware offloads, and data consistency needed to provide a coherent, cluster-wide view of memory that can unlock PMEM’s full potential.
About the Speaker:
Kevin Deierling leads the development of Mellanox’s solutions and partnerships in enterprise data center, cloud, big data, and storage. He also represents Mellanox at conferences and in standards bodies where he evangelizes high-speed interconnect technologies and efficient virtualized networks. He has previous experience as Chief Architect at Silver Spring Networks (a startup involved in networking electric meters), VP Marketing and Business Development at SpansLogic (a startup involved in network acceleration), and VP Product Marketing at Mellanox. Deierling has managed teams for developing core strategies in networking, cloud, SDN, big data, virtualization, and storage. He has contributed to several technology standards through organizations such as the InfiniBand Trade Association and the PCI Industrial Computer Manufacturing Group (PICMG). He holds over 25 patents in areas such as networking, wireless, security, and video compression, and was a contributing author of a text on BiCmos design. Deierling holds a BA in Solid State Physics from UC Berkeley.
About Mellanox:
More information is available at Mellanox.com
5:40-6:10pm
Gopal Hegde photo
OPEN - Keynote 6: How Workload Optimized SoC Processors Can Revolutionize Cloud Computing
Speaker: Gopal Hegde, VP/GM Server Processor Group, Cavium
Introduction: Rich Castagna, VP Editorial, TechTarget
Abstract:
Cloud applications differ greatly from traditional enterprise IT and require a different approach to computing. They require a high level of scalability, compute power, and memory bandwidth/latency, as well as the ability to support specific workload needs such as high-performance networking, the latest security methods, application acceleration, high-speed I/O, and massive amounts of storage. New workload optimized SoC processors designed specially to meet all these needs deliver improved performance while reducing system cost and power consumption. Such SoCs designed for the cloud thus make cloud computing the logical approach for future enterprise needs.
About the Speaker:
Gopal Hegde is the VP/GM of the Data Center Processor Group at Cavium, responsible for ThunderX line of processors. Gopal has over 22 years of experience driving business, technology and product innovations in silicon, software and systems. Gopal joined Cavium from Calxeda where he was the COO. Gopal revamped Calxeda solutions team and moved the company to an ODM-driven and workload specific model for delivery of ARM based servers. Prior to Calxeda, Gopal worked at Cisco as Senior Director of Engineering responsible for Cisco's UCS platforms. Prior to Cisco, Gopal worked for Adaptec and Intel. At Intel, he served as the GM of Ethernet switching division in Intel Communications group. Later as Chief Architect of IO for Intel Server Platforms, Gopal led the development of technologies enabling integration of PCIe into SandyBridge CPUs, IO virtualization for servers, Data Center Bridging (DCB), Backplane Ethernet and Fiber Channel over Ethernet (FCoE). Gopal holds MSECE from University of Massachusetts at Amherst, and ME from Indian Institute of Science, Bangalore, India.
About Cavium:
More information is available at Cavium.
7:00-8:30
OPEN - Beer, Pizza and Chat with the Experts
Organizers: Ajay Dubey, System Architect, Altera & KRS Murthy, CEO, I Cubed
Table Leaders:
Big Data
KRS Murthy, CEO, I Cubed
Networking
Arkadiy Shapiro, Sr Technical Marketing Engineer, Big Switch Systems
Cloud Computing
Arkadiy Shapiro, Principal Technical Marketing Engineer, Big Switch Systems
25/40/50/100/200/400 GbE NVMe
Scott Feller, Associate VP Product Marketing, Inphi; Das Sharma, Sr Principal Engineer/Director, Intel
Fabrics
Devashish Paul, Director Strategic Marketing – Systems Solutions, IDT
High-performance computing
Axel Kloth, CEO, SSR Labs
Hyperconvergence
Ajay Dubey, System Architect, Altera
Marketing
Lee Stein, Consultant, Stein Writes
Power and cooling
Brian Zahnstecher, Principal, PowerRox
POWER Architecture
Norman James, Lead Engineer OpenPOWER Enablement, IBM; Calista Redmond, Director OpenPOWER Global Alliances, IBM/President, OpenPOWER Foundation
Scale-out servers
Kumar Sankaran, Associate VP Software and Platforms, AppliedMicro; Parag Jain, Associate VP Processor Products, AppliedMicro
Security
Rich Fetik, CEO, Data Confidential
Silicon photonics
Brad Smith, Director Marketing Interconnects, Mellanox Technologies
Application acceleration
Debasish Pratiher, Lead Technical Marketing Engineer, Cavium
SSDs
Hubbert Smith, Strategy/Business Development Director, Samsung Semiconductor
Employment
Tanya Freedman, VP Group Services, Connetics Communications
End users
Jacob Hall, Sr VP/Innovation Wrangler (DROP Head of Wholesale Labs), Wells Fargo
Market Research
Mike Bruzzone, Industry Analyst, Camp Marketing
Mobile Edge Computing (MEC)
Cary Snyder, Consulting Engineer, E2E Wireless
Thursday, April 14th
8:30-9:45am
Session A-201: High-Performance Computing (Compute Track)
Organizers: Chris Piedmonte, CEO, Suvola; Paul Teich, Sr Analyst, Tirias Research
Chairperson: Rao Mikkilineni, Co-Founder/Interim CEO, C3DNA
Instructors:
Accelerating HPC Performance with Coprocessors and Very Large Memory Subsystems
Axel Kloth, CEO, SSR Labs
Challenges in Developing Applications for Heterogeneous Architectures on Server Systems
A.G. Karunakaram, CEO, MultiCoreWare
Description:
Developing high-performance computing platforms at reasonable cost remains a challenge. Current approaches include coprocessors, large memory systems (for in-memory computing), and leveraging diverse hardware computing elements including GPUs, DSPs, and FPGAs.
Intended Audience:
Hardware design engineers; engineering managers; product and product marketing engineers; storage engineers, specialists, and managers; data center engineers and managers; network engineers and managers; CIOs, CTOs, and infrastructure architects; IT managers; product planners and designers; VARs, OEMs, and solution providers; system analysts, engineers, and managers; market analysts; marketing managers and marketing engineers.
About the Chairperson:
Rao Mikkilineni is the Co-Founder and Interim CEO at C3DNA, a Silicon Valley startup, where he helps enterprise IT departments and infrastructure providers transition to cloud computing. C3DNA provides next generation IT distributed data center technologies and products dealing with end-to-end application availability, performance, and security operations and management. 

Rao has 30 years experience in the telecommunications and IT industries.  He has held senior research and management positions at AT&T Bell Labs, Bellcore, US West, Network Programs, SS8 Networks, LightSand Communications, and Hitachi Data Systems.  He also has worked at Courant Institute of Mathematical Sciences, Columbia University, and University of Paris.

Rao obtained a PhD in Physics from the University of California, San Diego, working with Nobel Laureate physicist Walter Kohn.   
8:30-9:45am
Session B-201: Silicon Photonics (Networking Track)
Organizers: Christos Kolias, Researcher, Orange Silicon Valley; Peter Christy, Research Director Networking, 451 Research
Chairperson: Jacob Hall, Sr VP/Innovation Wrangler, Wells Fargo
Panelists:
Bill DeVries, Director Marketing, Lumerical Solutions
Brice Achkir, Distinguished Engineer, Cisco
Brad Smith, Director Marketing Interconnects, Mellanox Technologies
Description:
Silicon photonics involves taking light, the world’s fastest communication technology, and building it directly into standard silicon-based CMOS semiconductor chips. Silicon photonics can deliver cost-effective optical connectivity at all levels of communications systems. Potential applications include data centers, high-performance computing, telecom networks, and commercial video systems. It is particularly important in applications with data rates above 10 Gbps where electrical circuits run into major signal integrity problems.

Issues in determining whether silicon photonics will succeed include light sources, cost-effective methods for getting light in and out of the chips, packaging, power, scalability, data rates, and distance limitations. A major current question is whether silicon photonics is ready to take on the challenge of 100GbE and whether chips can be produced with viable features and reasonable yields at market prices.
Intended Audience:
Hardware design engineers; engineering managers; product and product marketing engineers; storage engineers, specialists, and managers; data center engineers and managers; network engineers and managers; CIOs, CTOs, and infrastructure architects; IT managers; product planners and designers; VARs, OEMs, and solution providers; system analysts, engineers, and managers; market analysts; marketing managers and marketing engineers.
About the Chairperson:
Jacob Hall is Innovation Wrangler and Sr VP at Wells Fargo.  As part of the Corporation Innovation team he guides new technologies into and across teams within Wells Fargo.  Previously, he created a global lab for Wells Fargo that has successfully promoted a culture of innovation across the organization.  His efforts have contributed to new revenue, improved operational efficiency, delivered new business capabilities, and improved time to market.  He has also supported technology industry entrepreneurs, VC partners, and internal business teams through advisory and mentoring roles.  He has 20 years' experience in the financial industry including previous positions with Wachovia and First Union.  He holds a Certificate in Strategy and Innovation from MIT’s Sloan School of Management and a BS in Information Technology from Capella University.
8:30-9:45am
Session C-201: Customer Implementations of Open Networking (Networking Track)
Organizers: Uma Parepalli, Architect, SK Hynix Memory Solutions; Jonathan Hinkle, Director/System Platform Technologist, Lenovo
Chairperson: Jathin Ullal, Infrastructure Architect, Saygo
Panelists:
J.R. Rivers, CTO, Cumulus Network
Rajani Kolli, Director Core Infrastructure, Walmart Labs
Evan Parker, Product Management Leader, Calix Networks
Prakash Ramchandran, Sr Mobile Cloud Architect, Futurewei Technologies
Ajay Sahai, OpenNFV Partner Solutions Leader, HPE
Description:
Open source networking is now being implemented by customers and early adherents including clouds, megawebsites, telcos, and other advanced facilities. In this session, a variety of customers will discuss why they chose to implement open networking, how the implementations went, what problems they encountered, how they proceeded, and what products and advances they would like to see from vendors.

They’ll cover issues such as funding, transitions, personnel buy-in, legacy applications, performance, management, and hints and warnings.
Intended Audience:
IT technologists, managers and executives, administrators, operators, technical and product marketing, product managers. CIOs, CTOs, and infrastructure architects; product planners and designers; VARs, OEMs, and solution providers; system analysts, engineers, and managers; market analysts; marketing managers and marketing engineers.

Typical questions for the panel will include:
  • How could an Open Networking/Network Virtualization add value or enhanced value to the customer?
  • What should be the approach of a customer deploying Open Networking / Network Virtualization?
  • What are the challenges being faced today by customers adopting ON/NV?
  • Where do you see the principal use cases for Open Networking in scalable infrastructure today? How does this compare to a year ago and what do you think will change in the next year and five years out?
About the Chairperson:
Jathin Ullal is an infrastructure architect with Saygo. He has global experience in designing, deploying, supporting and marketing data networking and telecom infrastructure, He has been responsible for over 80 cloud offerings across private, public and managed clouds based on OpenStack and Cloud Foundry. He has been part of early teams at networking companies including open source based Infoblox and HP, Cisco, Nortel. He is an MSEE from University of New Mexico.
10:00-11:00am
Session A-202: Infrastructure (Compute Track)
Organizers: Chris Piedmonte, CEO, Suvola; Paul Teich, Sr Analyst, Tirias Research
Chairperson: Rich Fetik, CEO, Data Confidential
Instructors:
Rack-Scale Architecture Advancements
Murugasamy Nachimuthu,Principal Engineer, Intel
IO Processors Speed up Software-Defined Infrastructures
Benoit Ganne, Research Engineer, Kalray
Commodity Hardware with Hyperscale Power Systems
John Meinecke, CEO, EDCS Power
New Semiconductor Technology Leads to More Efficient Server Power Supplies
Stephen Cash, Sales/Marketing Manager, Itochu Plastics
Description:
Data center infrastructure continues to improve, although often in the background compared to bigger attention-grabbers. New types of processors continue to appear, while racks and power supplies take on new forms and new levels of integration. Power is an area of major interest, as power supplies generally consumer much of a data center’s energy budget. Improved versions can reduce energy bills considerably without requiring large-scale redesigns or performance tradeoffs.
Intended Audience:
Data center architects, server hardware designers, systems engineers, systems analysts and integrators, marketing and product engineers and managers, engineering managers, technology managers, test engineers, network and server managers and engineers; computer and datacenter managers and engineers; infrastructure managers and specialists.
About the Chairperson:
Rich Fetik is CEO and founder of Data Confidential, a security consultancy focusing on system reliability, reduced operating and support costs, and data confidentiality. Mr. Fetik has recently patented a design for a customizable storage controller supporting both software-defined storage and a security model for in-situ HPC. Parts of Big Data algorithms then run on the storage devices instead of on servers, reducing latency and increasing performance.
10:00-11:00am
Session B-202: Cloud Computing (Networking Track)
Organizers: Christos Kolias, Researcher, Orange Silicon Valley; Peter Christy, Research Director Networking, 451 Research
Chairperson: Casey Quillin, Director, Dell’Oro Group
Instructors:
Automatic Resilience Engineering in Cloud  Computing
Vipul Shivnani, Graduate Student, San Jose State University,
Creating Operating Environments that Span Clouds and Physical Infrastructures
Rob Hirschfeld, CEO, RackN
Description:
Clouds are a critical aspect of data centers today. Most centers are sending more and more of their work to clouds, particularly public ones like those provided by Amazon and Microsoft. So most new server sales are going to clouds, and many of the servers in data centers now direct work to and from clouds. Applications must generally use both local resources and cloud resources, thus requiring ways to deal with either or both locations transparently.
Intended Audience:
Cloud developers and managers; data center managers and engineers; hardware and software designers; network engineers and managers; communications and networking specialists; system architects and engineers.
About the Chairperson:
Casey Quillin is Director for Network Security, Data Center Appliance, and Storage Area Network Market Research at Dell’Oro Group. He has over 18 years experience as an executive manager and entrepreneur in the technology sector. Before joining Dell’Oro Group in 2011, he was VP Engineering at Snapfish, the world’s largest online photo-sharing site; CTO of Oasys Networks, an application service providers; and Co-Founder and CEO of Logic by Design, an interactive media agency. He holds an MS in Finance from Georgia State University and an MBA from St. Mary’s College.
10:00-11:00am
OPEN - Session C-202: POWER to the People: OpenPOWER Revolutionizes Server Capabilities
Organizers: Calista Redmond, Director OpenPOWER Global Alliances, IBM/President, OpenPOWER Foundation
Panelists:
Calista Redmond, Director OpenPOWER Global Alliances, IBM/President, OpenPOWER Foundation
Norman James, Lead Engineer OpenPOWER Enablement, IBM
Description:
The widely-proven POWER architecture offers high-performance server processors aimed at applications in big data, high-performance computing, real-time analytics, clouds, video and image processing, genomics, and virtual reality. It works with the latest high-speed memories and with specialized processors such as GPUs, ASICs, and FPGAs. Furthermore, it is now part of the OpenPOWER infrastructure, which allows for collaborative development at every level from chips through the software stacks. Many servers and workloads are already taking advantage of the POWER architecture, and designers can create a wide variety of systems that combine leading-edge processing power with the extensive OpenPOWER ecosystem. With hundreds of server projects underway, momentum is incredible. Come see how the POWER architecture is creating a REVOLUTION in servers.
Intended Audience:
Hardware design engineers and engineering managers; systems engineers and architects; cloud developers and managers; data center managers and engineers; hardware and software designers; network engineers and managers; communications and networking specialists.
About the Organizer:
Calista Redmond is President of the OpenPOWER Foundation and Director of OpenPOWER Global Alliances at IBM. She leads strategic relationships including commercialization strategies, development and business projects, and primary matchmaker to opportunities across the OpenPOWER community. Calista serves as IBM’s director on the OpenPOWER Board with a mission to guide the community and help it advance the POWER architecture in the industry. Her background includes promoting open source initiatives including OpenDaylight and OpenPOWER, and working on many acquisition and divestiture missions and several strategic alliances. Before joining IBM, she was an entrepreneur with four successful IT startups. She holds an MBA in Strategy and Management in High Technology from the University of Michigan and a BS in Communications from Northwestern University.
About the Instructor:
Norman James is currently the Lead Engineer for OpenPOWER Enablement at IBM, where he is the design lead for OpenPOWER and is training the application engineers who will support it. He has over 15 years experience with the POWER architecture and is the top resource person for designers evaluating POWER or planning to use it in their applications. As the leader in developing the POWER systems roadmap, he has created new methods for system design, test, and review and has initiated a new leadership organization that combines program management, chief engineers, and chief architects. He is a frequent speaker at conferences and other events and works with companies worldwide to broaden the POWER ecosystem. Mr. James holds a BSEE from Texas A&M University and an MSEE from the University of Texas at Austin.
11:00-11:30am
Dolly Wu photo
OPEN - Keynote 7: Today’s Open Platforms for Hyperscale Datacenters
Speaker: Dolly Wu, GM Datacenter/Cloud USA, Inspur Systems
Introduction: Jean S Bozman, VP/Principal Analyst, Hurwitz & Associates
Abstract:
Many open hardware platforms are currently available, including OCP (Facebook implementation), Scorpio Project Designs (Open Datacenter Designs for China), and Intel (Rack Scale Architecture). Each has advocates among hyperscale datacenters that have deployed them in volume. Cloud designers must be aware of the differences among them and must understand which is most suitable for specific types of private cloud, public cloud, and hybrid cloud implementations.
About the Speaker:
Dolly Wu is the GM of Inspur Systems’ Datacenter/Cloud Division, where she is in charge of opening the US and Canadian markets for the company. She has over 20 years experience in the high technology industry working with data centers, CSPs, direct end user customers (in financial services, Internet/cloud, life sciences, and media/entertainment), VARs, system integrators, OEMs, and government and education customers. Her focus is currently on the big data, cloud computing, HPC, and storage market segments. She has previous experience with Synnex/Hyve Solutions, Newisys Data Storage (a Sanmina company), Supermicro, and Everex. She holds a BS in Business Administration from the University of California at Berkeley.
About Inspur Systems:
More information is available at Inspur Systems.
11:30am-Noon
Rob Peglar photo
OPEN - Keynote 8: Speed Up Your Applications with 3D XPoint Technology
Speaker: Rob Peglar, VP Advanced Storage, Micron Technology
Introduction: Casey Quillin, Director, Dell’Oro Group
Abstract:
An obvious problem in application design for big data is that storage is too far away from the processor. Hard drives take so long to access (up to 100,000 times longer than DRAM) that the whole system slows down. Designers must expend a lot of effort either avoiding storage accesses or trying to mask them with other activity. The new 3D Xpoint technology (jointly developed by Intel and Micron) brings storage much closer. It can reduce the difference to as little as 80 times today and 20 times in the near future. The result is to create new approaches for system architects and to enable entirely new applications involving enormous data sets and real-time analysis. Areas of interest include the Internet-of-Things (IoT), genome mapping, and virtual reality
About the Speaker:
Rob Peglar is Vice President, Advanced Storage at Micron Technology, and a member of the Storage Business Unit’s five-person global leadership team. The unit, with $3-plus billion dollars annual revenue, provides solid state disk (SSD) and other non-volatile memory products such as 3D NAND and 3D Xpoint. Rob leads a team directing partner and customer-facing collaborations for future designs of advanced storage systems and data-intensive-computing solutions. His team is focused on using non-volatile memory technology to solve difficult problems in machine learning, data analytics, scale-out computing design, and several other key areas. Rob is a 39-year veteran of the storage industry, published author, and frequent industry speaker at leading storage and cloud-related seminars and conferences worldwide.

He was previously CTO Americas for EMC Isilon, responsible for customer-facing scale-out NAS technology requirements, designs, and implementations. Rob’s team directed hundreds of strategic customer engagements, spanning multiple product releases and integrated solutions stacks. He focused on solutions for big data/analytics, media and entertainment, life sciences, EDA, oil and gas, financial services, and other vertical market workloads. His team pioneered the first customer deployments of the Hadoop Filesystem (HDFS) embedded in a scale-out NAS platform.

He has also been a Senior Fellow and VP Technology at Xiotech, principal storage architect for StorageTek, and Manager of UNIX Development for ETA Systems. Rob is a member of the Board of Directors of the Storage Networking Industry Association (SNIA) and a member of the Program Executive Committee for the Flash Memory Summit. He is a three-time member of the EMC Elect (2014-2016) and was selected for the CRN Storage Superstars Award in 2010.

Rob holds a BS in computer science from Washington University (St. Louis) and did graduate work there.
About Micron:
More information is available at Micron.com.
Noon-12:30pm
Brad Booth photo
OPEN - Keynote 9: Is It Time for Optics to the Server?
Speaker: Brad Booth, Sr Engineer, Microsoft
Introduction: KRS Murthy, CEO, I Cubed
Abstract:
At 10 Gb/s and above, electrical signals cannot travel beyond the box unless designers use expensive, low-loss materials. Optical signaling behaves better but requires costly cables and connectors. For 25 Gb/s technology, datacenters have been able to stick with electrical signaling and copper cabling by keeping the servers and the first switch together in the rack. However, for the newly proposed 50 Gb/s technology, this solution is likely to be insufficient. The tradeoffs are complex here since most datacenters don’t want to use fiber optics to the servers. The winning strategy will depend on bandwidth demands, datacenter size, equipment availability, and user experience.
About the Speaker:
Brad Booth is a long-time leader in Ethernet technology development and standardization. Currently heading up the 25/50G Ethernet Consortium and the Consortium for On-Board Optics, he is a Principal Engineer at Microsoft, where he leads the development of hyper-scale interconnect strategy for Microsoft’s cloud datacenters. He is also the founder and past Chairman of the Ethernet Alliance. Brad was previously a Distinguished Engineer in the Office of the CTO at Dell Networking, where he developed Dell's next generation server-storage-networking fabric strategy. He has also held senior strategist and engineering positions at Applied Micro, Intel, and PMC-Sierra. The holder of 16 patents related to networking technologies, he has received awards from the IEEE Standards Association for work on Ethernet standards and awards for his contributions to Gigabit Ethernet, 10 Gigabit Ethernet and Ethernet in the First Mile. He was listed as one of the 50 most powerful people in networking by Network World magazine.
About Company:
More information is available at Microsoft.com.
2:30-3:00pm
Linley Gwennap photo Paramesh Gopi photo
OPEN - Keynote 10: ARM-based Servers: A Market and Product Update
Speakers: Linley Gwennap, President, The Linley Group and Dr. Paramesh Gopi, President & CEO, Applied Micro Circuits Corporation
Abstract:
After garnering initial attention in 2012, 64-bit ARM-based servers have been continuously improving performance while proving out their reliability and capabilities in the market. Large-scale data centers are showing invigorated interest in ARM-based servers, especially for memory-intensive web-scale workloads as well as storage and networking applications. As a leading independent industry analyst, Mr. Gwennap will discuss his view of data center demand for ARM-based processors as well as his opinions regarding the required performance characteristics ARM-based servers will need to demonstrate to facilitate wide-scale adoption.

Dr. Gopi will discuss X-Gene® 3, AppliedMicro’s flagship processor in his presentation “X-Gene 3: Performance with Maturity.” During his presentation, Dr. Gopi will reveal performance and power characteristics for X-Gene 3. Dr. Gopi will also explain how the the evolution of the X-Gene family of processor products makes it the only multi-generation, field-tested, enterprise-hardened ARM-based processor in the market, both currently and for the foreseeable future.
About the Speakers:
Linley Gwennap is the president of The Linley Group. One of the most respected analysts in the microprocessor industry, he has followed the industry for more than 20 years. Starting as a processor designer at Hewlett-Packard, Linley later worked in PA-RISC marketing and then became editor-in-chief of Microprocessor Report and vice president of MicroDesign Resources before founding The Linley Group in 1999.
Dr. Gopi joined AppliedMicro as Senior Vice President and Chief Operating Officer in 2008 and was appointed President and Chief Executive Officer and Board Member in 2009. From September 2002 to June 2008, he was with Marvell Semiconductor, where he served as Vice President and General Manager of the Embedded and Emerging Business Unit. At Marvell, Dr. Gopi held several executive-level positions including Chief Technology Officer of Embedded and Emerging Business Unit and Director of Technology Strategy. Dr. Gopi has over 50 patents to his credit and received the 2011 Lauds & Laurels Distinguished Alumnus Award from The Henry Samueli School of Engineering at UC, Irvine. He holds a doctorate degree in Electrical and Computer Engineering at the University of California, Irvine.
About The Linley Group:
More information is available at LinleyGroup.com
About tApplied Micro:
More information is available at AppliedMicro.com
3:00-4:15pm
OPEN - Session A-203: Investment Trends in Venture Capital (Compute Track)
Organizer: Brian Wilcove, Partner, Artiman Ventures
Chairperson: Chris Piedmonte, CEO, Suvola
Panelists:
Brian Wilcove, Partner, Artiman Ventures
Angel Orrantia, Business Development Director, SKTA Innopartners
Chris Rust, Independent Early Stage Investor
Gaurav Tewari, Managing Director, Citigroup Ventures
Description:
The $50 billion server market has been a productive area for startups. Opportunities exist today in both hardware and software, and include chips, peripherals, accelerators, systems software, and packaging, as well as management tools and utilities. Issues include the emergence of scale-out servers (microservers), integration of networking into the server CPU, network and storage virtualization, software-defined storage and software-defined data center, SDN and NFV, the impact of combining storage with the compute function, the rise of solid state storage, big data solutions, and server interconnect beyond 10GbE.
Intended Audience:
Current or future entrepreneurs, technologists, design engineers, engineering managers, server designers, systems engineers, systems analysts and integrators, marketing and product engineers and managers, technology managers, business development managers, marketing and marketing communications specialists, and financial analysts.
About the Organizer:
Brian Wilcove is as Partner focusing on early-stage technology investments at Artiman Ventures. His current investments include Discern, Enovix, Guavus, Runnable and Virsec. His previous investments include BayPackets (acquired by GenBand), Calix (IPO NYSE:CALX), ConteXtream (acquired by HP), Internet Photonics (acquired by Ciena), KXEN (acquired by SAP), Loglogic (acquired by Tibco), OnFiber (acquired by Qwest) and Tele  Atlas (acquired by TomTom). His areas of interest include communications and networking, business intelligence, and energy technologies.

Before joining Artiman, he spent twelve years in venture capital at Sofinnova Ventures and TeleSoft Partners. Previously, Brian co-founded Virtela (acquired by NTT), a managed global cloud provider. He also created, launched, and managed Qwest Communications’ Internet product portfolio, which he grew from zero to over $1B of annual revenue. Brian began his career at ANS (America Online).
About the Chairperson:
Chris Piedmonte is CEO of Suvola, a company focused on creating enterprise-class software and offering engineering and consulting services for scale-out servers. He was previously cofounder and CTO of Algebraix Data, and founder/CEO of XSPRADA, where he developed enterprise data management software. He was also founder/CEO of Eagle Creek Systems, which he built into a multimillion-dollar software engineering business. He holds 8 patents in data management. An expert in software technologies such as object-oriented analysis and design, applications and systems design, and development and project management, he has a BSEE from the Rose-Hulman Institute of Technology.
3:00-4:15pm
Session B-203: High-Speed Interfaces (Networking Track)
Organizers: Christos Kolias, Researcher, Orange Silicon Valley; Peter Christy, Research Director Networking, 451 Research
Chairperson: Brian Zahnstecher, Principal, PowerRox
Instructors:
Accelerating 25G/40G Ethernet with TCP Offload
Kelly Masood, CTO, Intilop
Open RANs Become Mobile Superhighways
Cary Snyder, Consulting Engineer, E2E Wireless
A New Standard to Handle a Variety of Ethernet Rates
Shre Shah, Data Center Architect, Xilinx
Using 25/40/50/100 GbE in Storage Deployments
John Kim, Director Storage Marketing, Mellanox Technologies
Description:
Interface rates continue to increase for both wireless and wired systems, leading to a proliferation of data rates and standards. Ethernet now has a wide range of standards above 10G, including 25, 40, 50, and 100G with more to come. There are so many variants that a standard now exists allowing designs to handle whatever may be out there. The reasons behind the sheer number include the difficulty of implementing electrical signaling at such high frequencies, the need to match data rates with available signaling speeds, the high cost of moving to higher standards and supporting multiple standards, and the number of new technologies involved at all levels. One simple way to increase Ethernet bandwidth without moving to a higher data rate standard is to simply offload the burdensome TCP overhead.
Intended Audience:
Communications engineers; hardware design engineers and managers; product planners and designers; network engineers and managers; communications and networking specialists; system architects and engineers
About the Chairperson:
Brian Zahnstecher is a Principal at PowerRox, where he focuses on power design, integration, system applications, and OEM market penetration for power electronics. He has successfully handled assignments in system design/architecting, AC/DC front-end power, embedded solutions, processor power, and digital power solutions for a variety of clients. He offers complete, end-to-end power services covering design support, troubleshooting/debug, quality, reliability, manufacturing, technical sales/marketing support, market definition, and logistics. He previously held positions in power electronics with industry leaders Emerson Network Power, Cisco, and Hewlett-Packard, where he advised on best practices, oversaw product development, managed international teams, and designed and optimized voltage regulators. He has been a regular industry contributor as an invited speaker, author, workshop participant, session host, roundtable moderator, and volunteer. He has over 12 years of industry experience. He holds Master of Engineering and Bachelor of Science degrees from Worcester Polytechnic Institute.
3:00-4:15pm
OPEN - Session C-203: Providing Storage at Memory Speed Using NVDIMMs (sponsored by the SNIA NVDIMM SIG) (Storage/Performance Track)
Organizer: Arthur Sainio, Sr Director Marketing, SMART Modular Systems
Chairperson: Bill Gervasi, Memory Technology Analyst, Discobolus Designs
Instructors:
Bill Gervasi, Memory Technology Analyst, Discobolus Designs
Mat Young, VP of Marketing, Netlist
Bob Frey, Sr. Director of Engineering, SMART Modular Technologies
Description:
NVDIMMs are persistent memory modules that reside on the DDR DRAM channel, combining volatile DRAM and nonvolatile flash memory. Under normal power conditions, an NVDIMM operates just like DRAM with ultra low latency and essentially infinite endurance, but is still nonvolatile. During a power failure or system crash, the data in the DRAM is transferred to the flash and can be restored when normal conditions resume.

Persistent memory enables applications to run faster due to greater I/O performance. Typical areas of interest include databases, Web 2.0, analytics, OLTP, and video and image processing.
Intended Audience:
Systems analysts and engineers; computer, network, and data center engineers; storage, communications, and server specialists; cloud computing specialists; engineering managers; technology managers; test engineers; performance analysts
About the Organizer:
Arthur Sainio is Director of Product Marketing at SMART Modular Technologies, where he drives new product launches and business development activities for memory products. Involved in memory technology for over 20 years, he has been focused on NVDIMM products recently. He is an active contributor in the SNIA NVDIMM SIG and is a frequent speaker at industry trade shows. He holds an MBA from San Francisco State University and an MS from Arizona State University.
About the Chairperson:
Bill Gervasi is a well-known memory technologist and consultant. He has worked on the definition of DDR (double data rate) DRAM since its inception. He has introduced several DDR3 registered DIMMs into the JEDEC standardization process. He has also served on the JEDEC Board of Directors and chaired several JEDEC memory-oriented committees.

He worked for Intel for 19 years as a system hardware designer, a software designer, and a field accounts manager. He has previous experience with S3, Transmeta, Netlist, and SimpleTech. He has provided expert testimony in court cases involving patent disputes. Bill also speaks often at technology trade shows and offers training in memory technology. He holds a patent for a high-density memory module.
4:30-5:45pm
OPEN - Session A-204: Future of Open Servers and Open Storage (Compute Track)
Organizers: Chris Piedmonte, CEO, Suvola; Paul Teich, Sr Analyst, Tirias Research
Chairperson: Jean S Bozman, VP/Principal Analyst, Hurwitz & Associates
Panelists:
Chris Piedmonte, CEO, Suvola
Jonathan Hinkle, Director/System Platform Technologist, Lenovo
Chris DePuy, VP, Dell’Oro Group
Jacob Hall, Innovation Wrangler, Wells Fargo
Marc The’berge, Director Rack Solutions, Supermicro
James Leach, Director Platform Strategy, Cisco Systems
Description:
Server and storage form factors are changing -- and so is the mix of components housed inside the enclosures. This session will focus on the evolution of server and storage design -- how "dense" future servers and storage elements will become (form factors), how "close" server and storage components will become, how much memory (including flash) they will carry in the future -- and more. It will also discuss the open specifications for hardware and software that will likely become standards for future generations of servers and storage. We have already seen server and storage design change rapidly in recent years, but this panel will look ahead at what else is on the horizon. What new designs are anticipated and what types of workloads will they run?
Intended Audience:

Hardware and software designers and managers, engineering managers, server designers, systems engineers, systems analysts and integrators, marketing and product engineers and managers, technology managers, test engineers, telco and enterprise end users, consultants, design and communications specialists, data center, network, or computer system engineers and technologists, and design service providers.

Typical questions for the panel will include:

  • How are form factors going to change over the next three years? What do you foresee for scale-out servers, blades, and other emerging packages?
  • How will server and storage components be combined -- in different ways-- in future generations of servers?
  • How short will server and storage product lifecycles become over the next 3-5 years?
  • What role will flash play in future servers and storage systems designed for applications involving analytics and in-memory databases?
  • What about the role of fabrics, intelligent storage, and distributed systems?
About the Chairperson:
Jean S. Bozman is currently Vice-President and Principal Analyst at Hurwitz and Associates, where she covers data center infrastructure, server and storage technology, software-defined storage, and software-defined infrastructure (SDI). She also serves as Program Chairperson for the Software-Defined Infrastructure Summit. Before joining Hurwitz and Associates, she was Director of Infrastructure Research at Neuralytix, where she covered all aspects of datacenter infrastructure, and Senior Product Marketing Manager at SanDisk, where she drove the discussion of enterprise workloads that leverage SSDs.

A well-respected IT professional with over 20 years experience covering the worldwide markets for operating environments, servers and the workloads that run on servers, she was previously a Research VP at IDC. While at IDC, she focused on the worldwide market for server operating systems. She analyzed the worldwide server market and managed the Clustering and Availability Software (CLAS) market research.

Ms. Bozman has been widely quoted in business publications, including BusinessWeek and Investors Business Daily; in daily newspapers, including the San Jose Mercury News and Los Angeles Times; and in online publications, such as CNET (news.com), Bloomberg, and Reuters.

Ms. Bozman holds a B.S. from the State University of New York (SUNY) at Stony Brook and a master's degree from Stanford University.